1. Field of the Invention
The present invention relates to a high speed comparator used in microprocessor cache memories and translation look-aside buffer (TLB) devices.
2. Description of the Prior Art
In conventional microprocessors, plural bit comparators are used for cache memory tagging and for TLBs. One example of a conventional 24-bit comparator used as a cache memory tag unit is shown in FIG. 14. The tag memory 1401 is accessed by the input address PA 1410 (PA represents physical address), which is decoded by the decoder 1402. When the word line WL 1411 voltage is HIGH, the data stored in the memory cell array selected by the HIGH word line WL 1411 is output to the bit line pair thereof. When the sense enable line SEN 1412 becomes HIGH, the data from the tag memory is read out as address B [23:0] by the sense amplifier 1403. Here, [23:0] indicates that there are 24 bit lines 0, 1, 2, . . . , 23 for address B.
Each bit in address A [23:0] 1413 from the central processing unit (CPU) and B [23:0] is compared in the coincidence circuit 1404 for detecting whether the bit line signal from address A and the corresponding bit line signal from address B coincide with each other, or not. The coincidence circuit 1404 is formed by an exclusive NOR (XNOR; logical inverse of the exclusive logical sum) gate, and the coincidence/non-coincidence of all corresponding bits is detected by the AND circuit 1405. The hit signal line HIT 1414 becomes HIGH when all bit lines are coincident, and LOW when one or more bit lines is non-coincident. The cache memory RAM controls data input/output using this bit line signal.
The precharge/equalization circuit 1406 is controlled by the precharge enable PCEN 1415 and equalize enable EQEN 1416 signals to precharge and equalize the bit line pairs when the tag memory is not accessed. An N-channel MOSFET device is used as the precharge circuit to increase the speed of the read and precharge/equalization operations.
The write circuit 1407 for writing data W [23:0] 1418 is controlled by the write enable WEN 1417 signal.
A differential sense amplifier using a bipolar transistor with a high transconductance (gm) is used as the sense amplifier circuit 1403 to achieve a high read speed in the memory circuit. An example of this differential sense amplifier is shown in FIG. 15.
Referring to FIG. 15, the bit line pair B 1511 and NB 1512 are the inputs to the emitter follower circuits 1501, 1502. Two NPN transistors 1503, 1504 form the differential sense amplifier. The current-switching N-channel MOSFET 1505 operates only when the sense enable signal 1515 is HIGH, and operates then as a constant current supply device. A load resistance 1506, 1507 is provided for each differential sense amplifier, and data is output to the data output 1516.
In general, a circuit built with bipolar transistors has a low input impedance. A high base current is output when the bipolar transistor is saturated, and the load on the circuit connected to the base, i.e., the bit line, increases. As a result, there is the danger of the wrong data being written to the memory cell when there is much noise signal in the power supply or ground line because there will be a significant voltage drop even with the HIGH bit line during memory reading. Since the emitter follower circuit has a high input impedance, low output impedance, and high current gain as shown in FIG. 15 (1501, 1502), the emitter follower circuit is used to avoid this by reducing the bit line load. In addition, because a voltage that is the internal voltage Vbe between the base and emitter less than the bit line voltage is input to the base of the NPN transistor in the differential sense amplifier, the differential sense amplifier NPN transistor is not as easily saturated.
With the prior art as described above, three steps must be completed before the bit signal is generated, specifically, (1) tag reading, (2) per-bit coincidence/non-coincidence comparison of the address B [23:0] read from the tag memory and the address A [23:0] from the CPU, and (3) coincidence/non-coincidence comparison of all bits. As a result, this increases the time required between reading from the tag memory and hit signal generation. In particular, the number of gates and the delay time both increase because the multiple-bit data signal is compacted to a 1-bit signal in steps (2) and (3).
Furthermore, the addition of an emitter follower circuit increases the number of bipolar transistors, and thus increases the size of the sense amplifier. The effective size of bipolar transistors requiring a separation area between other bipolar transistor cannot be reduced as much as MOSFET devices can, even when the degree of integration increases, and it therefore becomes impossible to keep the memory cells and sense amplifiers proportionally reduced sized. As a result, it is not possible to provide a large-scale sense amplifier for each bit in a TLB or tag memory requiring simultaneous reading of many bits.